2021 IEEE International Solid- State Circuits Conference (ISSCC) | 2021
An Echo-Cancelling Front-End for 112Gb/s PAM-4 Simultaneous Bidirectional Signaling in 14nm CMOS
Abstract
The rapid growth of hyperscale data centers has led to an increased demand for high-speed and low-latency data connectivity solution upgrades, which are power-efficient and minimal cost. In the last few years, PAM-4 modulation across copper channels was realized by high-performance electrical transceivers in a tight signal integrity environment, which employed the superior spectral efficiency of PAM-4 over NRZ signaling. This shift created a relatively smooth path from 28Gb/s NRZ to 56Gb/s PAM4 per lane by keeping the same baud rate, which eliminated the need to replace the legacy communication channel components with high-performance cables and connectors, providing a cost-effective solution to the overall system. To achieve 112Gb/s, solutions employed channel components which require a doubling of signal bandwidth, thus increasing system cost [1,2]. While such solutions commonly use two separate channels per lane, one for transmit (Tx) and one for receive (Rx), this paper demonstrates the utilization of simultaneous bidirectional Tx and Rx across each individual channel such that 112Gb/s can be achieved per lane while maintaining the 28Gbaud rate and thereby the legacy, low-cost copper channels (top of Fig. 11.8.1).