2021 IEEE International Solid- State Circuits Conference (ISSCC) | 2021

28.4 A 400mVpp 92.3 dB-SNDR 1kHz-BW 2nd-Order VCO-Based ExG-to-Digital Front-End Using a Multiphase Gated-Inverted Ring-Oscillator Quantizer

 
 
 
 

Abstract


Next-generation wearable devices will enable clinical-grade, continuous ExG (ECG, EEG, EMG, etc.) biopotential monitoring, providing medical professionals with valuable longitudinal data outside of hospital settings. These devices must be ultra-low power $(\\lt 10 \\mu W)$ to enable long battery life while accurately digitizing sub-kHz, $\\mu V-$level ExG signals in the presence of large motion and/or stimulation artifacts $(\\gt 100$ mV) with high input-impedance $(Z_{in}\\gt 10M\\Omega)$ to avoid signal attenuation. Achieving such performance with conventional PGA + ADC architectures is challenging due to the conflicting low-power and $\\gt 90$ dB dynamic-range (DR) requirements [1]. To address this, several direct digitization analog front-ends (AFEs) have been reported [2]–[4]. While these offer wide DR, they typically have low input-impedance $(\\lt 5 M\\Omega)$ and/or low power-efficiency (FoM $\\le 172$ dB). This paper presents a scalable $2^{nd}-$order voltage-controlled oscillator (VCO)-only $\\Delta \\sum$ ADC that achieves 92.3dB SNDR in a 1kHz bandwidth using a mismatch tolerant, multiphase gated-inverted ring-oscillator (GIRO) quantizer with dynamic power-scaling. The ADC uses an impedance-booster to maintain $\\gt 50 M\\Omega$ input-impedance over the entire bandwidth while consuming $4.25 \\mu W$ during nominal operation and $5.8 \\mu W$ in the presence of artifacts resulting in an FoM of 174.7dB.

Volume 64
Pages 392-394
DOI 10.1109/ISSCC42613.2021.9365985
Language English
Journal 2021 IEEE International Solid- State Circuits Conference (ISSCC)

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