2021 IEEE International Solid- State Circuits Conference (ISSCC) | 2021

10.3 A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shaping SAR Quantizer

 
 
 
 

Abstract


Emerging communication and radar applications place enormous demands on ADC performance by requiring wide BW (100MHz) and high DR (70dB). Continuous-time delta-sigma modulators (CT-DSM) [1–2] are a mainstream solution as they deliver high amplifier efficiency, are easy to drive, and provide innate anti-aliasing. However, CTDSMs have some inherent drawbacks: 1) the loop filter is typically based on RC time-constants which are poorly defined and require digital tuning; 2) they do not scale with sampling frequency; and 3) they are very sensitive to DAC ISI and jitter [2]. Discrete-time (DT) DSMs, such as the emerging noise-shaping (NS) SAR architecture, avoid these problems, but cannot provide the essential benefits of CT-DSMs. We propose the new hybrid-loop (HL) DSM architecture, which combines the advantages of both CT and DT DSMs and eliminates the drawbacks. Moreover, a bandpass, time-interleaved noise-shaping (TINS) SAR quantizer [3] further boosts the new architecture’s performance. The prototype HL-DSM provides 68dB SNDR over a 100MHz BW for a quadrature input, without any calibration or tuning, while occupying only 0.09mm2 and consuming 13mW at 1.6GS/s. The resulting 166dB FoMS shows the potential of the HL-DSM as a more robust and practical alternative to CT-DSM.

Volume 64
Pages 167-169
DOI 10.1109/ISSCC42613.2021.9366006
Language English
Journal 2021 IEEE International Solid- State Circuits Conference (ISSCC)

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