2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) | 2019
An Approximate Multiply-Accumulate Unit with Low Power and Reduced Area
Abstract
Approximate computing benefits applications that are, to some extent, error tolerant with regard to accuracy by trading power for accuracy. In this paper, a low-power approximate multiply-accumulate (MAC) unit with reduced area is proposed. In the proposed MAC unit, a multiplier and an adder are merged in an approximate multiplier by distributing all accumulated sums to partial product rows. Experimental results demonstrate that, compared to a conventional MAC unit, the unsigned design of the proposed unit reduces power consumption and circuit area by 42.6% and 46.1%, respectively, without impacting accuracy significantly. While most approximate circuits do not handle signed numbers represented by two s complement effectively, evaluations using handwritten digit recognition on LeNet-5 indicate that the signed design of the proposed unit is sufficient for practical use.