Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out Analysis

Abstract

The test of digital circuits has benefitted greatly from the adoption of logical fault models and automatic test pattern generation (ATPG) tools targeting them. The cyclic process of defects in newer technology nodes being increasingly missed out by gross fault models and newer fault models being developed to better target them in silicon has continued, and EDA tools have evolved to provide new automation capabilities. This paper presents silicon results on one of Texas Instruments new safety critical products which show unique defect detection with patterns targeting newer fault models like small delay defects (SDD) and cell aware faults (CAF), and RAM Sequential (RAM-S) ATPG patterns for memory faults. The net defective parts per million (DPPM) recovered using these methods is 72. Based on these results, recommendations for coverage targets and the order in which these faults must be targeted are provided. The unique silicon fall-out data presented in this paper provides a strategy for very low (zero) DPPM test of digital systems-on-chips (SoCs) in advanced technology nodes.