Reliability of Package on Package (PoP) Assembly Under Thermal Cycles

Abstract

Stack electronic packaging technologies have now been widely implemented to increase the capabilities of commercial electronics in order to overcome the limitation of die fabrication with extremely finer features. The 3D packaging consists of stacking of packaged devices called package-on-package (PoP) and stacking of die within a package. This paper presents the test matrix for various 3D PoP packaging assembly configurations and reliability characterizations performed under accelerated thermal cycling (ATC) and accelerated extreme harsh thermal shock cycling (ATSC) conditions. The ATC and ATSC were performed in the range of−55°C to 125°C and −100°C to 125°C, respectively. Extreme cold temperature exposure at −100°C is representative of mild deep space environment whereas possibly none for industrial application. A design of experiment (DOE) technique was used to cover four methods of packaging stack assemblies and their effect on the stack packaging assembly reliability. The four methods are: (1) the top package with flux/bottom with tin–lead (SnPb) solder paste, (2) top/bottom both had solder paste, and (3) pre-stack package as a unit with SnPb solder and then assemble the stack package onto PCB with SnPb solder paste. In addition to daisy-chain resistance evaluation monitoring, non-destructive techniques including X-ray, scanning electronic microscopy (SEM), and optical images, as well as destructive methods by X-sectioning, were performed and presented for the as-assembled and after-thermal-cycles.