A CMOS Test Chip With Simple Post-Processing Steps for Dry Characterization of ISFET Arrays

Abstract

ISFETs (ion sensitive field effect transistors) are ion solid-state sensors based on MOSFETs (metal oxide semiconductor field effect transistors) applied in many areas including ion imaging, detection of viruses and bacteria and DNA sequencing. ISFETs implemented in standard CMOS technology adopt the inherent Si3N4 passivation as the sensing layer, and benefit from a high integration level with no need of post-processing steps. However, this implementation is associated with non-idealities such as output temporal drift, capacitive attenuation of the input signal and random offsets in the threshold voltage due to trapped charges. Most of these non-idealities, which require better understanding, are characterized through biasing a reference electrode immersed in a solution in contact with the passivation layer. To remove electrochemical effects from the measurements, this paper proposes a dry test where the wet test setup is replaced with a sputtered gold thin film that provides electrical contact with the ISFETs. Dry tests were performed in arrays of n-ISFETs and p-ISFETs from chips fabricated in a standard 180 nm high voltage CMOS technology. The intra-die threshold voltages of the n-ISFETs and p-ISFETs presented, on average, similar offsets, but their die-to-die fluctuation was high. Wet tests on an n-ISFET and a p-ISFET of two non-metalized chips indicated sensitivities of 38 mV/pH and 46 mV/pH, respectively. The dry test introduced herein allows the electrical parameters of ISFETs to be determined without the interference of chemical contributions as well as the charges trapped in the passivation layer to be estimated.