IEEE Journal of Solid-State Circuits | 2019

A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC



This paper presents a 12-b, 1-GS/s ADC array, realized by time-interleaving four 250-MS/s pipelined SAR ADCs, with integrated on-chip reference voltage buffers. A reference ADC-based calibration algorithm treats static nonlinearity, gain, and offset errors in the array. Timing-skew errors between the sub-ADCs are distinguished from those of the gain mismatches by the assistance of an analog high-pass filter (HPF) for input slope information and subsequently corrected by digitally controlled delay lines (DCDLs). Directly driven off the on-chip 50- $\\Omega $ termination resistors without any dedicated input buffer, the 65-nm CMOS prototype ADC array also employs a frequency-hopped, randomly-sampling scheme for the ref. ADC, eliminating the spectral effect of its interference to the main array. The core ADC consumes 31.5 mW and occupies an area of 0.27 mm2, including nine on-chip reference voltage buffers, the ref. ADC, and the HPF path. The measured peak signal to noise and distortion ratio of the array is 65.3 dB, and the measured spurious-free dynamic range is >70 dB from dc to 500 MHz at 1 GS/s with calibration. The prototype ADC chip achieves an figure of merit of 20.9 and 59.7 fJ/step (the latter is limited by the jitter of an off-chip clock source) for a low-frequency input and a Nyquist input, respectively.

Volume 54
Pages 2207-2218
DOI 10.1109/JSSC.2019.2915583
Language English
Journal IEEE Journal of Solid-State Circuits

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