A 15.1-mW 6-GS/s 6-bit Single-Channel Flash ADC With Selectively Activated 8× Time-Domain Latch Interpolation

Abstract

A selectively activated 8<inline-formula> <tex-math notation= LaTeX >$\\times $ </tex-math></inline-formula> time-domain (T-domain) latch interpolation is proposed for low-power high-speed flash analog-to-digital converters (ADCs). Flash ADCs with T-domain latch interpolation perform voltage-to-time (V-to-T) and time-to-digital (T-to-D) conversions along with conventional voltage-to-digital (V-to-D) conversion. This reduces the number of dynamic comparators (CMPs) of the V-to-D conversion for low power consumption. A conventional 4<inline-formula> <tex-math notation= LaTeX >$\\times $ </tex-math></inline-formula> T-domain latch interpolation that obtains 2 bits in T-to-D conversion reduces the number of dynamic CMPs to 17 from the conventional 63 in a 6-bit flash ADC. To further reduce the number of dynamic CMPs, the nonlinearity of the V-to-T conversion is resolved in this work. A large input is used to define a wide linear range in the V-to-T conversion, and only the linear range is used for an 8<inline-formula> <tex-math notation= LaTeX >$\\times $ </tex-math></inline-formula> interpolation. This enables a 3-bit T-to-D conversion, and thus, the number of dynamic CMPs is reduced to ten in a 6-bit flash ADC. The large input also enables high-speed operation by mitigating the <italic>RC</italic> time constant requirement of dynamic CMPs. For low-power T-to-D conversion, only two of eight converters in the T-to-D conversion are selectively activated for a conversion cycle. The fabricated 6-bit ADC chip in 1-V 65-nm CMOS achieves a 6-GS/s sampling frequency, a 15.1-mW power consumption, a 31.18-dB SNDR, and an 85-fJ/conversion-step figure of merit.