Impact of Bottom-Gate Biasing on Implant-Free Junctionless Ge-on-Insulator n-MOSFETs

Abstract

In this letter, we have fabricated Ge-on-insulator (Ge-OI) junctionless (JL) n-MOSFETs via wafer bonding and epitaxial lift-off (ELO) techniques. We have evaluated the electrical characteristics of Ge-OI JL n-MOSFETs with different thickness of Ge channel carefully thinned by the digital etching. Furthermore, the impact of bottom-gate biasing on the Ge-OI JL n-MOSFET devices with different Ge channel thicknesses has been demonstrated. High effective electron mobility (<inline-formula> <tex-math notation= LaTeX >$\\mu _{\\text {eff}}$ </tex-math></inline-formula>) of 160 cm²/<inline-formula> <tex-math notation= LaTeX >$\\text {V} \\cdot \\text {s}$ </tex-math></inline-formula> was obtained from a Ge-OI JL n-MOSFET with an 18 nm-thick Ge channel and subthreshold slope (S.S.) of 230 mV/dec was extracted on an even thinner 10-nm-thick Ge-OI JL n-MOSFET. Also, due to the stronger coupling between the channel and bottom-gate, we demonstrated higher <inline-formula> <tex-math notation= LaTeX >${V}_{\\text {th}}$ </tex-math></inline-formula> tunability and improvement of <inline-formula> <tex-math notation= LaTeX >$\\mu _{\\text {eff}}$ </tex-math></inline-formula> by bottom-gate biasing.