2.6-GHz Integrated LDMOS Doherty Power Amplifier for 5G Basestation Applications

Abstract

This letter presents a compact output combining network for a packaged integrated asymmetric Doherty power amplifier (DPA) by taking advantage of device drain source capacitance, Cds and package parasitic components. A new method is introduced to/of/for absorbing part of the peaking amplifier’s <inline-formula> <tex-math notation= LaTeX >$C_{\\mathrm{ ds}}$ </tex-math></inline-formula> into the impedance transformer, thus extending the <inline-formula> <tex-math notation= LaTeX >$C$ </tex-math></inline-formula>–<inline-formula> <tex-math notation= LaTeX >$L$ </tex-math></inline-formula>–<inline-formula> <tex-math notation= LaTeX >$C$ </tex-math></inline-formula>-based “<inline-formula> <tex-math notation= LaTeX >$C_{\\mathrm{ ds}}$ </tex-math></inline-formula>-absorption” technique to two-way asymmetric DPAs. Based on the proposed combining network, a two-stage laterally-diffused metal-oxide semiconductor (LDMOS) integrated asymmetric DPA was designed and fabricated at 2.6 GHz. The fabricated RF integrated circuit (RFIC) is mounted in a quad flat no-lead (QFN) package. Under a single-tone continuous-wave (CW) signal at 2.6 GHz, the DPA achieves a peak power of 46 dBm, a linear gain of 31.7 dB, and a 48% power-added efficiency (PAE) at 8-dB output power back-off (OBO). The DPA also demonstrates good linearizability by meeting the 5G spectrum mask and achieving a digital predistortion (DPD) corrected adjacent channel power ratio (ACPR) better than −51.5 dBc for 160-MHz long-term evolution (LTE).