IEEE Solid-State Circuits Letters | 2019
An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch
Abstract
An 8-bit 10-GHz <inline-formula> <tex-math notation= LaTeX >$8\\times $ </tex-math></inline-formula> time-interleaved SAR ADC in 28-nm CMOS incorporates an aggressively scaled DAC with grouped capacitors in a symmetrical comb structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A dual-path bootstrapped switch decouples critical signal from nonlinear capacitance to boost the sampling SFDR by more than 5 dB. The ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21 mW, yielding an FoM of 37 fJ/conv.-step, the lowest among the reported ADCs with similar speeds and resolutions and more than <inline-formula> <tex-math notation= LaTeX >$2\\times $ </tex-math></inline-formula> improvement from the state-of-the-art.