A 39 GHz T/R Front-End Module in 65nm CMOS

Abstract

Targeting at 5G communication, this paper presents design and analysis of a differential 39GHz T/R front-end module (FEM) in a 65nm CMOS process. The circuit consists of one stage cascode power amplifier (PA) and one stage common-source low noise amplifier (LNA), with two different switches for the receiver and transmitter functionality. To reduce the insertion loss and improve the transmitter output power performance, the switch is co-designed with the power amplifier output matching network. In the LNA input, three coupled inductors are used to realize the simultaneous noise and compact broadband impedance matching. In the receiver mode, the FEM achieves a measured gain of about 2.6dB, and a noise Figure (NF) of about 5.6dB. In the transmitter mode, the FEM achieves a measured gain of about 6.1dB while demonstrating 1dB compression output power (OP1dB) of 6.5 dBm with corresponding power added efficiency (PAE) of 14.7 %. The core area of the circuit is only 0.35mm2.