2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) | 2019

Group IV/oxide semiconductor bi-layer tunneling FET

 
 
 

Abstract


We have proposed and demonstrated a novel bi-layer tunneling FETs (TFETs) composed of group IV semiconductor (Si, SiGe, Ge)/oxide semiconductor type-II hetero-junctions, where the group IV and oxide semiconductors work as source and channels, respectively, of TFETs. The simulation study has revealed that (Si, Ge)/ZnO TFETs can exhibit extremely-steep sub-threshold slope of ~ 1 mV/dec with Ion of ~100 μA/μm order. The operation of bi-layer ZnO(ZnSnO) / Ge(Si) TFETs with TiN/Al2O3 gate stacks has experimentally been demonstrated. The high Ion/Ioff ratio of ~6×108 and the S.S. value of 71 mV/dec have been obtained at room temperature for the p-Ge/ZnO and the p-Si/n-ZnO TFET, respectively.

Volume None
Pages 1-3
DOI 10.1109/S3S46989.2019.9320690
Language English
Journal 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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