A Modeling Approach for 7nm Technology Node Area-Consuming Circuit Optimization and Beyond

Abstract

This work presents a novel statistical-based general compact model for 7nm technology node devices like FinFETs. Unlike conventional compact model based on less accurate elements including one-dimensional Poisson equation for three-dimensional devices and analytical equations for short channel effects, quantum effects and other physical effects, the general compact model combining few TCAD calibrated compact models with statistical methods can eliminate the tedious physical derivations. The general compact model has the advantages of high accuracy, strong scaling capability, good robustness and excellent transfer capability. It is demonstrated that the performance of 6 $T$ SRAM and RC control ESD power clamp through the trade-off between two key design knobs of FinFET can be improved extremely with implementation of the newly proposed general compact model. This framework is also suitable for path-finding researches on 5nm node gate-all-around devices, like nanowire FETs, nanosheet FETs and beyond.