2019 6th International Conference on Signal Processing and Integrated Networks (SPIN) | 2019

Linearity Analysis of Gate Engineered Dopingless and Junctionless Silicon Nanowire FET

 
 
 
 
 
 

Abstract


This paper demonstrate the comparative study of various linearity as well as intermodulation distortion (IMD) parameters for junctionless (JL) and charge plasma (CP) dopingless nanowire FETs with dual material gate (DM). The various parameters considered for analysis includes higher order transconductance coefficients: gm2 (second-order) & gm3 (third-order), second-third order harmonic distortion HD2 &HD3, third order current intercept point (IIP3), third order IMD (IMD3), higher order voltage intercept points (VIP2 & VIP3) etc. The simulation study results reveals that analog parameters namely transconductance gm and transconductance gain factor (TGF) along with cut-off frequency fT are better for CP_DM. The other parameters including Cgg, gm3, HD2, HD3, IIP3 and VIP3 for JL_DM shows enhanced performance over CP_DM.

Volume None
Pages 215-219
DOI 10.1109/SPIN.2019.8711788
Language English
Journal 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)

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