A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew Calibration

Abstract

This brief presents a 10-bit 600 MS/s 4-channel time-interleaved (TI) successive approximation register analog-to-digital converter (ADC). A background calibration algorithm using Lagrange polynomial interpolation is introduced to calibrate timing skew. It consists of digital detection and adaptive derivative-based correction, employing low filter taps and resulting in hardware reduction. Two reference voltage generators are implemented on-chip to provide a stable reference voltage for the sub-ADCs, enhancing the reliability and robustness of the circuits. The TI-ADC prototype is fabricated in the 65-nm CMOS process and occupies an area of 0.69 mm2. The measurement results show that at a sampling rate of 600 MS/s the ADC achieves a 49-dB SNDR after calibration while dissipating 34 mW from a 1.2/2.5-V supply.