High Efficiency and Small Group Delay Variations 0.18- $\\mu$ m CMOS UWB Power Amplifier

Abstract

A new staggered tuning technique, by optimizing the inter-stage matching circuit, is proposed to realize a power amplifier (PA) with small group delay (GD) variations and excellent gain flatness across the full bandwidth of ultra-wideband (UWB) system. The proposed PA consists of two stages where the first stage is constructed by a current-reuse with shunt RC feedback topology to realize gain flatness and low power consumption. The design is implemented in 0.18 <inline-formula> <tex-math notation= LaTeX >${\\mu }\\text{m}$ </tex-math></inline-formula> commentary metal-oxide semiconductor (CMOS) technology, fabricated, and tested. The proposed PA has a measured power gain (<inline-formula> <tex-math notation= LaTeX >${|{\\mathrm{ S}}_{21}|}$ </tex-math></inline-formula>) of 11.5 ± 0.7 dB, maximum power-added efficiency (PAE) of 26% and an output 1-dB compression point of 9 dBm, respectively, and this is the maximum PAE among CMOS PAs that cover the full bandwidth of UWB system. Besides, the PA has a small GD variations of ± 68 ps which is the lowest till date.