Low-Power Ternary Multiplication Using Approximate Computing

Abstract

We propose a novel approximate computing technique for low-power ternary multiplication. A carry-truncated ternary multiplier, error compensation circuits, and <inline-formula> <tex-math notation= LaTeX >$2 \\times 2$ </tex-math></inline-formula> ternary multipliers with various accuracies are proposed using the low-power design methodology with carbon nanotube FETs. An accuracy-configurable design method is proposed to design energy-efficient <inline-formula> <tex-math notation= LaTeX >$6 \\times 6$ </tex-math></inline-formula> approximate ternary multipliers. The energy benefit of the proposed <inline-formula> <tex-math notation= LaTeX >$6 \\times 6$ </tex-math></inline-formula> approximate ternary multipliers have been verified using <italic>HSPICE</italic> simulation. The proposed approximate design shows 82.8% power-delay product with 41.8% mean absolute percentage error improvement over the previous approximate multiplier-based design. Image processing applications are conducted using the proposed approximate designs to confirm that the accuracy of ternary multiplication is satisfied the user’s requirement.