An 85-MHz-BW ASAR-Assisted CT 4-0 MASH $\\Delta\\Sigma$ Modulator With Background Half-Range Dithering-Based DAC Calibration in 28-nm CMOS

Abstract

This paper presents a continuous-time 4-0 MASH <inline-formula> <tex-math notation= LaTeX >$\\Delta \\Sigma $ </tex-math></inline-formula> modulator with high power efficiency for wide-bandwidth wireless communication systems. An asynchronous successive-approximation-register (ASAR) is used as the quantizer in the <inline-formula> <tex-math notation= LaTeX >$\\Delta \\Sigma $ </tex-math></inline-formula> modulator to reduce the power consumption and to cancel the comparator mismatch of the conventional flash quantizer. An on-chip background half-range dithering-based calibration technique is proposed to improve the multi-bit feedback digital-to-analog converter matching, with limited overhead cost in terms of power consumption and area. To alleviate the metastability error of the ASAR and to increase the bandwidth, a zero-order loop is added to further quantize the intrinsic quantization error of the ASAR. The design is fabricated in a 28-nm bulk CMOS process. Clocked at a frequency of 1.7 GHz, the modulator achieves 68.5-dB SNDR and 83.6-dB spurious-free dynamic range over an 85-MHz bandwidth, while consuming 23.9-mW power, leading to an excellent Walden figure-of-merit of 64.9 fJ/step and a Schreier figure-of-merit of 164 dB.