A Reduced Architecture for ReRAM-Based Neural Network Accelerator and Its Software Stack

Abstract

Neural network (NN) accelerators based on resistive random access memory (ReRAM) have been widely investigated as a promising solution to address the <italic>memory wall</italic> challenge, due to its capability of <italic>processing-in-memory</italic> with extremely high density. However, the performance of these accelerators is bounded by the peripheral circuits and the interconnection. And they also suffer from accuracy issue and flexibility issue caused by the device-variation and the <italic>in-situ</italic> computation mode respectively. Solving these issues with hardware will further offset the performance. Enlightened by the design principle of conventional reduced instruction set computer (RISC), this article proposes a new software/hardware system for ReRAM-based NN acceleration, which achieves complex functions with sophisticated software tools while making the hardware much more compact and efficient, in order to fully utilize ReRAM potential. The hardware architecture, Field Programmable Synapse Array (FPSA), provides high-density reconfigurable logic, wires, and computational resources based on ReRAM-crossbar. Accordingly, the software can convert various types of NNs, including dynamic NNs, into equivalent networks that meet hardware constraints with negligible accuracy loss and optimize the scheduling and mapping of the latter onto FPSA. Further evaluations show that compared to one state-of-the-art ReRAM-based NN accelerator, PRIME, our approach achieves up to <inline-formula><tex-math notation= LaTeX >$1000\\times$</tex-math><alternatives><mml:math><mml:mrow><mml:mn>1000</mml:mn><mml:mo>×</mml:mo></mml:mrow></mml:math><inline-graphic xlink:href= ji-ieq1-2988248.gif /></alternatives></inline-formula> speedup.