Compact Model Strategy of Metal-Gate Work-Function Variation for Ultrascaled FinFET and Vertical GAA FETs

Abstract

In this paper, we develop an accurate compact model for work-function variation (WFV)-induced threshold voltage <inline-formula> <tex-math notation= LaTeX >$({V}_{\\textsf {th}})$ </tex-math></inline-formula> variations of various 5-nm candidates, in this case, Si SOI FinFETs, vertical gate-all-around nanowire FETs, and nanoplate FETs. Using the typical probability distribution function model to predict the effect of WFV, due to the ideal condition, an error occurs in ultrascaled devices. Therefore, to analyze the influence of WFV accurately, the error rate (<inline-formula> <tex-math notation= LaTeX >$\\alpha $ </tex-math></inline-formula>) is corrected by considering irregular grain patterns (Voronoi method). In addition, the total number of grains on the metal surface can be calculated while considering the effective grain size and gate area due to the structural characteristics of the device. Finally, the model is benchmarked against 3-D TCAD simulations to demonstrate excellent accuracy [1.53% error in <inline-formula> <tex-math notation= LaTeX >$\\sigma $ </tex-math></inline-formula>(<inline-formula> <tex-math notation= LaTeX >${V} _{\\textsf {th}}$ </tex-math></inline-formula>)]. Moreover, the accuracy is improved by more than 15 times compared with the existing analytical models. As a result, the proposed model based on binomial distribution is able to analyze the effect of WFV at a significantly lower computational cost than 3-D TCAD simulations.