Reconfigurable Ferroelectric Transistor–Part II: Application in Low-Power Nonvolatile Memories

Abstract

In Part I, we proposed reconfigurable ferroelectric transistors (R-FEFETs) with a unique property of dynamic modulation between the volatile (logic) and nonvolatile (memory) modes of operation with the help of a control signal. They showcase excellent robustness in the presence of gate leakage with larger hysteresis in the nonvolatile mode with respect to ferroelectric FETs (FEFETs) and higher ON current in the volatile mode compared with standard FETs. Using the unique attributes of R-FEFETs presented in Part I, we explain the dynamics of transition between various modes of operation for circuit-level applications in this paper. We propose a 3T nonvolatile memory design that offers significant power savings over FEFET-based memories by virtue of the control terminal. Our analysis shows that the proposed R-FEFET memory exhibits 55% lower write power and 37%–72% lower read power at iso access time and 33% lower area compared with a recently proposed standard FEFET-based memory.