Record GmSAT/SSSAT and PBTI Reliability in Si-Passivated Ge nFinFETs by Improved Gate-Stack Surface Preparation

Abstract

This article reports Si-passivated Ge nFinFETs with significantly improved Gm_SAT/SS_SAT and positive bias temperature instability (PBTI) reliability enabled by an improved replacement metal gate (RMG) high-<inline-formula> <tex-math notation= LaTeX >${k}$ </tex-math></inline-formula> last process. SiO₂ dummy gate oxide (DGO) deposition on Ge fin is shown to form (Si_{<italic>x</italic>})Ge_{1-<italic>x</italic>}O_{<italic>y</italic>}, which is, compared to a pure SiO₂, more difficult to remove completely during the dry clean prior to the gate-stack formation. By extending the DGO removal clean, improved PBTI reliability, reduced <inline-formula> <tex-math notation= LaTeX >${D}_{{\\text {IT}}}$ </tex-math></inline-formula>, and increased electron mobility are demonstrated. Moreover, by suppressing the Ge channel oxidation through the choice of less-oxidizing DGO or inserting an Si-cap layer prior to the DGO deposition, a greatly improved long-channel electron mobility is obtained at a scaled fin width. Finally, together with the PBTI maximum <inline-formula> <tex-math notation= LaTeX >${V}_{{\\text {OV}}}$ </tex-math></inline-formula> of 0.13 V, the best Gm_SAT/SS_SAT of 5.4 is achieved, which is today’s record value among the sub-100-nm-<inline-formula> <tex-math notation= LaTeX >${L}_{g}$ </tex-math></inline-formula> n-channel Ge Fin and gate-all-around nanowire FETs. These results clearly show the importance of the pre-gate-stack channel surface preparation on the scaled Ge FinFETs to benefit from a previously optimized Si-passivated Ge gate-stack.