650-V 4H-SiC Planar Inversion-Channel Power JBSFETs With 55-nm Gate Oxide: Relative Performance of Three Cell Types

Abstract

Planar 650-V 4H-silicon carbide (SiC), inversion-channel, 55-nm gate oxide junction barrier Schottky field effect transistors (JBSFETs) with three types of cells are compared in this article for the first time. Devices with linear, hexagonal, and octagonal layouts were fabricated in a commercial foundry. The JBS diode was integrated within each cell type. The Schottky contact width for the JBS diode was adjusted to optimize third-quadrant ON-state voltage drop to below 2.5 V for each cell type to ensure by-passing the body diode while maintaining good blocking characteristics in the first quadrant. The hexagonal cell case was the only one whose breakdown voltage (560 V) fell below the 650-V rating. The highest breakdown voltage (710 V) was observed with the octagonal cell layout with a low leakage current of 10 nA at 600 V. The lowest specific ON-resistance was observed for the hexagonal cell design. However, its gate–drain charge was twice that of the conventional linear cell design and four times that of the octagonal cell design. The data from this work demonstrate that the best overall performance for the 650-V SiC, inversion-channel, 55-nm gate oxide junction barrier Schottky field effect transistors is achieved by using the octagonal cell design.