30-nm Contacted Gate Pitch Back-Gate Carbon Nanotube FETs for Sub-3-nm Nodes

Abstract

Carbon nanotube FETs (CNFETs) promise significant energy efficiency benefits versus silicon for digital systems. While these projected benefits are for CNFETs with similar geometries as silicon FETs (e.g., top-gate FETs, with the FET gate on top of the channel), the majority of the demonstrated CNFETs leverage back-gate geometries due to ease of fabrication (i.e., the gate is fabricated before and underneath the FET channel). Although back-gate CNFETs have already been experimentally demonstrated, importantly, there lacks any rigorous analysis of their benefits for digital very-large-scale integrated (VLSI) circuits. Here, we rigorously quantify, for the first time, the benefits of back-gate geometries: both for enabling aggressive device scaling as well as VLSI circuit energy-delay product (EDP) benefits. The key contributions of this paper are: 1) first analysis of back-gate FET geometries for digital VLSI circuits, showing they enable >1.6× additional EDP benefit for CNFETs due to reduced parasitic capacitances (versus top-gate CNFETs), 2) our analysis shows that leveraging back-gate FETs enables aggressive FET scaling to sub-3-nm technology nodes, and 3) as a feasibility case study, we experimentally realize digital logic circuits that fit within the world s smallest contacted gate pitch to date (CGP, a key metric defining the area of an FET and consequently the technology node) of 30 nm.