Split Parallel Semibridge Switching Cells for Full-Power-Range Efficiency Improvement

Abstract

This article proposes a positively coupled inductor (PCI) based paralleling scheme for basic semibridge switching cells, which are formed by power MOSFETs and diodes. Both the semibridge switching cells and the inductors are split into two parallel parts, and thus, a small differential mode (DM) inductance is formed between the midpoints of the parallel semibridge switching cells. A time-delay-based modulation strategy is applied to generate a controllable circulating current, which enables all active switches to achieve the zero-current switching (ZCS) or zero-voltage switching, and all diodes to achieve ZCS turn-off. Accordingly, the switching loss and the reverse-recovery loss can be significantly reduced. The operating principle of the proposed paralleling scheme is characterized by two complementary operation modes: desynchronized mode with soft-switching (lower switching loss) and synchronized mode with lower conduction loss. Compared with conventional soft-switching schemes, this solution features zero auxiliary switches, constant switching frequency, and improved full-power-range efficiency enabled by the dual operation modes. Furthermore, design guidelines of the PCI are presented where a novel winding arrangement is proposed and verified to obtain a controllable DM inductance. The operation principles and advantages of the proposed paralleling structure are comprehensively validated on both buck and boost dc–dc converters with Si/SiC power MOSFETs and diodes.