IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2021

A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing

 
 
 
 
 
 
 
 
 

Abstract


This article presents an <inline-formula> <tex-math notation= LaTeX >$8\\times 8$ </tex-math></inline-formula> lattice-reduction-aided (LRA) soft-output multiple-input multiple-output (MIMO) detector for Chinese enhanced ultrahigh throughput (EUHT) wireless local area network (LAN) standard. The preprocessing algorithm combining simplified-sorting Cholesky decomposition and low-complexity decoupled lattice reduction (LDLR) is proposed to reduce computational complexity and latency with parallelism improvement. In addition, K-best detection adopts a sorting-reduced strategy utilizing approximate ordered sequence. Compared with other published LRA K-best detection algorithms, simulation results show that our proposed algorithm has performance improvement. In addition, in order to save hardware resources, a folded K-best architecture and an optimized intermediate storage strategy are introduced. Furthermore, a fully pipelined VLSI architecture is designed in Semiconductor Manufacturing International Corporation (SMIC) 40-nm 1P9M technology to support the <inline-formula> <tex-math notation= LaTeX >$8\\times 8.64$ </tex-math></inline-formula>-QAM MIMO-OFDM system. The detector can achieve 3.85-Gb/s data throughput at 641-MHz clock frequency with 0.71-<inline-formula> <tex-math notation= LaTeX >$\\mu \\text{s}$ </tex-math></inline-formula> latency. The proposed detector is competitive in terms of latency, throughput, and area efficiency to state-of-the-art works and can meet the data-rate requirement of the EUHT standard.

Volume 29
Pages 307-320
DOI 10.1109/TVLSI.2020.3036822
Language English
Journal IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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