Comparison of 2-T FeFET Nonvolatile Memory Cells: Gate Select vs. Drain Select

Abstract

In this work, we compare two kinds of 2-T NVM cell designs based on Ferroelectric FETs (FeFETs) using SPICE and TCAD simulations. Our study indicates that, although the 2-T cell design with a pass-transistor separating the gate (Gate-Select) of FeFET from read/write path can achieve non-disturb write scheme, the effective write voltage of the FeFET is limited by the pass voltage and threshold voltage of the pass transistor and the memory window (MW) is reduced. For 2-T cell design with a selector sharing the drain side of FeFET (Drain-Select), this issue can be mitigated because the write voltage is directly applied to the FeFET. In addition, the negative pulse operation can be avoided by drain erase operation in the drain-select cell, which can save the complexity of peripheral circuitry. Moreover, in comparison with the gate-select cell, the maximum gate-to-source voltage of selector to avoid write disturb in drain-select cell is reduced to half, which may be better for the reliability.