2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID) | 2021

ISAMod: A Tool for Designing ASIPs by Comparing Different ISAs

 
 

Abstract


Designing the ISA (instruction set architecture) is a very critical activity in the entire ASIP (application-specific instruction set processor) design process. There is a long history of using automated tools that suggest custom instructions based on an analysis of the data flow graphs (DFGs) of target programs. Such approaches often create an ISA that is overspecialized for a small set of applications and they often suggest a plethora of custom instructions that cannot be practically implemented. A survey of recent work indicates that adding custom instructions to freely available ISAs such as RISC-V still relies on bespoke analyses and institutional memory. In this paper, we focus on such modern applications, where we only need to add a few instructions to an existing ISA such as RISC-V. The aim is to either supplant or complement the extensive manual analysis that goes into such decision making. We propose an unconventional approach that uses novel visualization techniques to first understand the impact of different ISA features by comparing the execution of the same program using different popular ISAs: both RISC and CISC. Our novel graphical methods provide simple and intuitive explanations for differences in performance across ISAs for the same micro-architecture. Moreover, we can use this information to pick desirable instructions from other ISAs and evaluate their impact when they are incorporated. We show examples where we are able to increase the average performance by 16.5 % for 6 SPEC-2017 benchmarks by just adding 2–10 extra instructions in the basic RISC-V ISA. The performance gain is comparable with state of the art custom instruction generators. Our tool, ISAMod (ISA Modify), achieves this using a very simple and intuitive approach. It has the potential to prove itself as a vital part of the overall design flow and can reduce reliance on institutional memory to a large extent.

Volume None
Pages 1-6
DOI 10.1109/VLSID51830.2021.00005
Language English
Journal 2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID)

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