A 5nm Wide Voltage Range Ultra High Density SRAM Design for L2/L3 Cache Applications

Abstract

The paper presents SRAM cache design in 5nm FinFET technology for L2/L3 cache applications, demonstrating circuit techniques to enable wide-range DVFS (Dynamic Voltage and Frequency scaling) operation. CPU L2/L3 SRAM cache must achieve higher density while meeting performance and power criteria defined for each operating performance point (OPP). 6-T High Density (HD) bitcell is the ideal bitcell choice to achieve cache density requirements. However HD bitcell needs write assist to ensure robust write across operating range. In this work an area efficient NBL write assist technique is implemented which deploys a circuit technique to operate boost capacitor at SRAM core voltage domain (Vsram). This NBL technique minimizes voltage variation across boost capacitor and help to address overboost and underboost concerns. A selftime scheme is also introduced in the work which is designed in a way to control selftime window depending on delay tracking from both SRAM core (Vsram) and periphery (Vperi) supplies. The scheme ensures adequate design margins with optimized performance across wide voltage range to satisfy performance and power requirements of CPU DVFS system. The techniques of Selftime tracking and NBL assist have been successfully implemented in a 5nm finfet SRAM testchip. Silicon results show all SRAM instances achieved 100% yield with a robust operating range from 0.45v-1.1v.