ZeroScreen: A Novel Structure for IC Reliability Screening at Time-Zero

Abstract

With technology approaching to 14nm and below, the shrinking gate size makes IC reliability become a big concern. As the speed of CMOS and FinFET is degraded by aging mechanisms including negative bias temperature instability (NBTI) and hot carrier injection (HCI). At the same time, significant process variations differ the aging degradation rate of each individual IC, which cause significant failure time differences even for the ICs belonging to the same lot. Therefore, to efficiently bin the devices into the reliability tiers for different safety & security usages, it is necessary to perform predictive reliability screening during production test at time-zero. In this paper, a novel on-chip architecture for fast time-zero predictive aging screening (ZeroScreen) is proposed. The screening time is limited to 8.14ms per device considering 50MHz test clock frequency and 6.6 µs automatic test equipment (ATE) level settling time. In the experiment, 185 fresh FPGA devices under test (DUTs) implemented with ZeroScreen are binned into 4 predictive reliability bins by ZeroScreen. By comparing with the 8-hour accelerated burn-in results, the reliability screening errors of ZeroScreen are less than 6.5% and 4.3% for static and dynamic stress cases, respectively.