Challenges of Designing Heterogenous (multi-PDK) Packages

Abstract

Given the complexity of today’s chips, packages and boards, ICs based on both silicon and non-silicon materials are now required to design optimal high-performance systems. As a result, engineers are integrating multiple heterogeneous technologies in a single product, which not only affects the performance and functionality of ICs but also introduces a new set of challenges for semiconductor companies. In 2017, Cadence announced a novel, front-to-back cross-platform solution that streamlines and automates the design of a package or module featuring off-chip devices and multiple ICs based on differing process design kits (PDKs).In addition to streamlining the front-to-back design of chips and packages, this solution allows IC designers the ability to seamlessly include system-level layout parasitics in the IC verification flow. This help to reduce design cycles by seamlessly combining package/board layout connectivity data with the IC layout parasitic electrical model. The resulting automatically generated “system-aware” schematic can then be easily used to create a testbench for final circuit-, system-level simulation. Previously, designers were only able to include system-level layout parasitics based on time-consuming ad hoc methods. By automating this entire flow, the new Cadence solution eliminates the highly manual and error-prone process of integrating system-level layout parasitic models back into the IC designer’s flow, reducing days of work to mere minutes.In late 2018, Cadence announced a partnership with National Instruments coupled to the second generation of this solution. The new solution further streamlines the concurrent design of multi-die systems and sub-systems while adding additional 3D electromagnetic (EM) extraction/modeling capabilities and additional capabilities for package/module-level layout. This effort takes designing chips, packages and boards to a whole new level…something we call “System Design Enablement”. This presentation will cover the current challenges of designing heterogenous packages/modules and provide an overview of the new Cadence Virtuoso RF Solution.