Post-Si Nano Device Technology

Abstract

Ge is one of the promising candidates for use as high mobility channels in future CMOS device. The mobility of an electron and a hole is much higher in the Ge channel than in the Si channel. On the other hand, for 10-nm-node CMOS and beyond, a multi-gate fin structure is utilized to maintain electrostatic controllability of the gate electrode. The Ge FinFET is generally fabricated by Ge epitaxial growth from a SiGe/Si substrate [1] and conventional top-down etching by a plasma etching [2]. Usually, fin structure formation in Ge Fin FETs is carried out by using ICP (inductively coupled plasma) sources. However, ICP sources cause plasma induced damages owing to the ultraviolet (UV) light generated from the ICP and charging-up phenomena by the irradiation of ionized atoms. One concern is that such etching damage reduces the performance and reliability of Ge-channel CMOS. In this work, to break-through these plasma-induced damages, we demonstrated defect-free and highly anisotropic Ge etching for Ge FinFET fabricated by C1 neutral beam etching [3].