Efficient Core Mapping on Customization of NoC Platforms

Abstract

Network-on-Chip (NoC) has been developed as an interconnect patterns in state-of-the-art multiprocessors. Core mapping and identifying suitable NoC platforms have a substantial effect on NoC system performance and corresponding costs. In this research work, investigated core mapping and optimization of NoC platforms by using an efficient algorithm. Consider two performance metrics (reliability and delay) and two cost metrics (area and power). The proposed mapping algorithm was assessed by applying it to different NoC benchmarks. The simulation results expose that the suggested mapping technique outperformed the other mapping techniques in terms of performance and cost metrics.