Design of Area Optimised, Energy Efficient Quaternary Circuits Using CNTFETs

Abstract

Currently there exist many Multi Valued Logic (MVL) based design methodologies for implementing ternary and quaternary circuits using Carbon Nanotube Field Effect Transistors (CNTFETs) optimized for low power and delay. One of the design approaches for MVL circuits is a Multiplexer (MUX) based approach, where transmission gates are used to pass the logic values. This paper presents a novel way to design optimized Quaternary Logic circuits where single N-type CNTFET or P-type CNTFET transistors are used for passing constant values instead of transmission gates, by adjusting their chirality vectors . This approach results in significant reduction in number of transistors required for the design. Quaternary Half Adder, Quaternary Full Adder and Quaternary One Digit Multiplier are implemented here using the proposed approach. Simulation results for the proposed designs show an improvement of upto 90% in power, upto 35% in delay and upto 37% in terms of number of CNTFETs for Quaternary Half Adder, upto 98% in power, upto 21% in delay and 45% in terms of number of CNTFETs for Full Adder and upto 98% in power, upto 68% in delay and 53% in terms of number of CNTFETs for One Digit Multiplier as compared to the designs existing in literature.