Efficient Test Compression Configuration Selection

Abstract

Test costs for large industrial designs increase rapidly in recent years. On-chip test compression hardware has become a pragmatic technology to cut down the overall test costs by reducing test data volume. Determining the input and output channel counts of test compression hardware that results in minimum test data volume is thus a critical issue. In this paper, efficient methods to estimate test pattern counts for an extensive range of input/output counts are developed. These methods require only a small number of ATPG runs. The estimation results can then be utilized to determine the test data volume for each input/output configuration. The configuration with the estimated lowest test data volume thus can be determined. The pattern count results of each configuration for a design can also be used to determine the best suitable configuration when the design is to be embedded in an SoC system.