A study of curvilinear routing in IN5 standard cells: challenges and opportunities (Poster Presentation)

Abstract

With the advent of Multi-beam mask writers, curvilinear shapes are being realized with comparable metrics to Manhattan shapes when it comes to write times which has been the main issue with conventional VSB mask writers. Techniques like PLDC also enhance Multibeam writing of complex curvilinear patterns. In the past Standard Cell (SDC) design was done with a gear ratio (polypitch/m1pitch) of 1:1. This inadvertently results in congestion on lower layers namely M1 as we try to push the design density. This can be improved by going to a gear ratio of 2/3 by which we derive additional M1 tracks (3 M1 tracks for every 2 poly) but the benefit derived out of a 2/3 gear ratio cell somewhat gets negated with the need for M2 in standard cells where MINT layer doesn’t fully cover M1. To resolve the problem with higher M2 usage in standard cells we can introduce 1.5D or curvilinear routing to make the final/minor routing connections. Here we try to present a study of different challenges and opportunities that arises as a result of introducing curvilinear routing in Standard cells (SDC). In IN5 technology node when we go for a gear ratio (CPP/M1Pitch) of 2/3 we observe that for every standard cell we will need two variants of the cell. These two variants have M1 which are interleaved and shifted. We can live with only one variant of the cell but this inadvertently leaves gaps in between standard cells as the M1 grids will not align when they are abutted. Further study of the impact of the need of two variants reveals that in some standard cells (~9% in IN5) we end up with using M2 for completing the connections. This has many drawbacks (extra routing resources, congestion on M2, increase in area and reduced performance) which negates the benefit derived with 2/3 gear ratio. To fix this problem we have two options. One is to use 1.5D routing and the other to use curvilinear routing. With this approach all the benefits of 2/3 gear ratio can be preserved (improved routing density, area and performance) without the need for M2. A design implementation of the same in IN5 AO22D2 standard cell with CPP of 45nm and M1 pitch of 30nm has been done and the M2 routing (with default approach) has been eliminated. Although this approach has numerous benefits and extended applications (in signal routing) it does present significant challenges when it comes to EDA tools, verification, mask and OPC. We are in the process of evaluating different test cases for design, mask and OPC challenges with curvilinear routing in IN5 SDC. On the design front the challenges include library characterization, PPA and runtime analysis, RC extraction and design verification. On the mask and OPC front some of the challenges include regular versus ILT OPC and their process window comparison, understand the SRAF’s required, mask data volume and MRC. A comprehensive understanding of the challenges and resolution of the same will entail a new scaling paradigm for standard cell designs and also enhance signal routing which in turn has numerous benefits when it comes to PPA.