A Pixel-Parallel Virtual-Image Architecture for High Performance and Power Efficient Graph Cuts Inference

Abstract

A Pixel-Parallel Virtual-Image Architecture for High Performance and Power Efficient Graph Cuts Inference Tianqi Gao, University of Illinois Urbana Champaign Rob A. Rutenbar, University of Pittsburgh Contact: [email protected] Graph Cuts is a popular technique for Maximum A Posteriori inference in computer vision. It transforms a Markov Random Field problem into a network flow problem, solved via the Push-Relabel algorithm. While attractively simple, the large size of a typical image and the large number of necessary pixel-level iterations render the technique computationally expensive. Prior accelerator attempts have been reported with GPUs and FPGAs. In [1], the first pixel-parallel architecture was demonstrated in FPGA, but limited to only 256-pixel images. This paper extends this pixel-parallel concept and makes following contributions: a Virtual Image architecture solves the size limitation: large images are decomposed into tiles , and stacked on the physical processor array; appropriate addressing mechanisms handle virtual pixels and a range of tile edge effects; scaling up the processor array to 1536 pixels; a novel and hardware-friendly heuristic shortens the convergence. We demonstrate the first working virtual-image Graph Cuts accelerator, applied to standard 640x480 images. Scaling up the hardware and the new heuristic bring 6.5x and 1.65x speedups respectively compared with [1]. The design is 7-20x faster than prior FPGA designs, and roughly comparable in speed to a modern GPU benchmark. However, the architecture also offers significant performance-per-unit-power advantages. Formulating a figure of merit particularly for Graph Cuts inference - Graph Cuts per second per Watt - our architecture is about 4 times better than other implementations. Keywords: FPGA; Machine learning; Hardware Acceleration; Computer Vision DOI: https://doi.org/10.1145/3289602.3293948