HOTMeTaL: Hardware Optimization Tool for Memory Table and Logic Conversion

Abstract

FPGA designs are typically optimized for speed and accuracy, with the amount of available hardware considered after the fact. Balancing speed, accuracy, and hardware utilization is a difficult proposition. In this paper, we demonstrate the Hardware Optimization Tool for Memory Table and Logic Conversion (HOTMeTaL) which helps with this tradeoff by modifying part or the majority of an existing FPGA design to use additional logic resources when memory is at a premium, or force the use of memory when logic is highly utilized; without significantly changing the overall functionality of the design. Using established minimization methods, traditionally used for programmable logic devices (PLDs), we also allow the conversion of groups or individual output bits into minimal logic circuits, which then allows the creation of several functionally identical designs, but allowing more control over the resources used in a design. After introducing the basics of the algorithm, we demonstrate the utility of this process with direct comparisons to examples from previous works. It is demonstrated that in some cases, our system will reduce the amount of logic (slices) while simultaneously removing the