Proceedings of the 2019 on Great Lakes Symposium on VLSI | 2019
LSM: Novel Low-Complexity Unified Systolic Multiplier over Binary Extension Field
Abstract
Unified (hybrid field-size) systolic multiplier over GF(2m) (binary extension field) has attracted significant attentions from research communities recently as it can be used in reconfigurable cryptographic processors. In this paper, we present a novel Low-complexity unified Systolic Multiplier (LSM) design strategy to address the above mentioned challenge. First, a novel multiplication algorithm for unified implementation is proposed first with detailed mathematical derivation. Then, an efficient systolic structure is then presented based on the proposed algorithm (with the help of several mapping techniques). Finally, a thorough complexity analysis is given to verify the superior performance of the proposed design (the proposed structure involves better complexities than the newly reported design).