Devise Rust Compiler Optimizations on RISC-V Architectures with SIMD Instructions

Abstract

Recently, Rust has become a popular system programming language and been widely used in microkernel OS designs, cryptocurrency designs, deep learning applications, and web browsers. Rust is designed for highly safe and concurrent systems and provides similar performance to C++. In the architecture work, RISC-V is with an open instruction set architecture in growing use due to its performance, power efficiency, and open architectures. Extension of ISAs in RISC-V is another advantage. Venders can select the extension ISAs to make the design more flexible. There is SIMD extension ISAs called V extension in RISC-V. However, currently Rust was not well-supported on RISC-V platforms. In this paper, we describe how to enable the Rust flow and framework based on LLVM infrastructure for RISC-V architectures with SIMD V extensions. For the basic infrastructure support, we enable two flows for RISC-V architecture. In addition, we also enable RISC-V SIMD instructions for Rust SIMD vector with LLVM support. In the experiment, we illustrate our code generation for Blas style matrix and vector computations for Rust on RISC-V V instructions. The experiment is run on the spike simulator which we implement the V extension for RISC-V architectures.