Random Number Generation from Internal LFSR and Fluctuation of Sampling Interval

Abstract

An unpredictable random number generator (URNG) adopts a deterministic algorithm with volatile internal states of a microprocessor, which makes the output of the URNG practically unpredictable. This study examines the URNG design proposed by Suciu et al., wherein performance counters are considered as entropy sources. Our experiments confirm that the URNG with performance counters requires a relatively long sampling interval with a background task to produce a high-quality random sequence. On this basis, we propose a new URNG design that is suitable for embedded systems. A simple 128-bit LFSR (Linear Feedback Shift Register) is built in a processor, whose lower 32-bit value is used as a random number. If an adequate sampling interval is maintained, the derived values pass the DIEHARD test.