Physics Based Analytical Modeling of Asymmetric Elevated Source Tunnel FET (AES-TFET) for Better Tunnel Junction Device (TJD) Performance

Abstract

\n In this paper, a two-dimensional analytical model for asymmetric elevated source tunnel field effect transistor (AES-TFET) has been developed to obtain better tunnel junction device performance. Device physics based analytical modelling is performed by solving 2-D Poisson’s equation. Surface potential distribution, electric field variation and band-to-band tunneling (B2B) rate have been investigated by this numerical modelling. In our proposed structure, the source has been elevated (varied 2 nm to 6 nm) to incorporate corner effect; which boosts the carrier transport via thin tunneling barrier, with controlled ambipolar conduction. This eventually produces better source-channel interface tunneling for a n-channel AES-TFET structure. 2-D numerical device simulator (SILVACO TCAD) has been used for simulation work. The simulated graphical representations have been finally validated by analytical modelling of AES-TFET.