Drain Current Recovery Time Analyses of InAlGaN/GaN HEMTs Realized with a Back-Barrier Buffer Layer

Abstract

This article presents the performances obtained on a $0.15 \\mu \\mathrm{m}$ gate length InAlGaN/GaN HEMT technology on SiC substrate. This technology uses a back-barrier buffer layer to ensure the confinement of electrons in the channel, which minimizes variations of the drain current when the HEMT devices are submitted to DC or RF pulses. Measurements of the drain current recovery time are shown when the devices are submitted to VDS, VGS or microwave RF pulses. A comparison with an AlGaN/GaN HEMT structure designed with an iron doped buffer layer is proposed.