A 75.8dB-SNDR Pipeline SAR ADC with 2nd-order Interstage Gain Error Shaping

Abstract

This paper presents a low-cost gain error shaping (GES) technique that can substantially suppress the in-band interstage gain error in pipeline ADCs. It works for both closed-loop and open-loop amplification. A prototype ADC with the proposed 2nd-order GES technique in 40nm CMOS achieves 75.8dB SNDR over 12.5MHz BW while operating at 100MS/s and consuming 1.54mW. It achieves 174.9dB Schreier FoM. The GES-related hardware occupies less than 2% of the core area.