A Hardware Efficient Elliptic Curve Accelerator for FPGA Based Cryptographic Applications

Abstract

The work presents an elliptic curve crypto accelerator to implement scalar multiplication on standardized NIST curve over Galois binary fields by using polynomial basis. The proposed design provides efficient hardware utilization and low power consumption. For this purpose, hybrid finite field multiplier is proposed using standard Karatsuba multiplier and shlft-and-add multiplication algorithms. The proposed hybrid finite field multiplier can perform one finite field multiplication in $\\frac{m}{2}$ clock cycles, with m being the key-length. Montgomery algorithm with projective coordinates (LopezDahab) is used for the computation of scalar multiplication. An FSM based control unit is developed, governing the overall operations of proposed accelerator. The proposed architecture has been modeled in Verilog-HDL and implemented up to place and route level using the Xilinx Vivado and ISE design software for various FPGA devices. The achieved results demonstrate the convenience of proposed ECC accelerator for resource constrained embedded systems applications requiring low area and low power hardware.