Exploration of Hardware Acceleration Methods for an XNOR Traffic Signs Classifier

Abstract

Deep learning algorithms are a key component of many state-of-the-art \nvision systems, especially as Convolutional Neural Networks (CNN) \noutperform most solutions in the sense of accuracy. To apply such \nalgorithms in real-time applications, one has to address the challenges \nof memory and computational complexity. To deal with the first issue, \nwe use networks with reduced precision, specifically a binary neural \nnetwork (also known as XNOR). To satisfy the computational requirements,\n we propose to use highly parallel and low-power FPGA devices. In this \nwork, we explore the possibility of accelerating XNOR networks for \ntraffic sign classification. The trained binary networks are implemented\n on the ZCU 104 development board, equipped with a Zynq UltraScale+ \nMPSoC device using two different approaches. Firstly, we propose a \ncustom HDL accelerator for XNOR networks, which enables the inference \nwith almost 450 fps. Even better results are obtained with the second \nmethod - the Xilinx FINN accelerator - enabling to process input images \nwith around 550 frame rate. Both approaches provide over 96% accuracy on\n the test set.