High-performance Pipelined FPGA Implementation of the Elliptic Curve Cryptography over GF (2n)

Abstract

In this paper, a high-performance area-efficient hardware design for the Elliptic Curve Cryptography (ECC) is presented, targeting the area-constrained high-bandwidth embedded applications. The high-speed design is implemented using pipelining architecture. The applied architecture is performed using n-bit data path of the finite field GF(2n). For the finite field operations, the implementation in the ECC uses the bit-parallel recursive Karatsuba-Ofman algorithm for multiplication and Itoh-Tsuji for inversion. A modified efficient montgomery ladder algorithm is utilized for the scalar multiplication of a point. The pipelined registers are inserted in ideal locations, where balanced-execution paths among computing components are guaranteed. A Memory-less finite state machine model is developed to control the instructions of computing the finite field operations efficiently. The high-performance design has been implemented using Xilinx Virtex, Kintex and Artix FPGA devices. It can perform a single scalar multiplication in 226 clock cycles within 0.63μs using 2780 slices and 360Mhz working frequency on Virtex-7 over GF (2163). In GF (2233) and GF (2571), a scalar multiplication can be computed in 327 and 674 clock cycles within 1.05μs and 2.32μs, respectively. Comparing with previous works, our design requires less number of clock cycles, and operates using less FPGA resources with competitive high working frequencies. Therefore, the proposed design is well suited in the resourcesconstrained real time cryptosystems like those in online banking services, wearable smart devices and network attached storages.