Effective Elimination of Analog Impairments Error in Parallel Interleaving Sigma Delta A/D Converters: A Recent Study

Abstract

The oversampling sigma delta modulators which produce one bit samples of input signals can be used to create AD converters, which can produce either multi bit samples of high resolution but with low sampling frequency, or low resolution samples with high sampling frequency. One of the methods of overcoming this limitation is based on using several converters operating in parallel in a time interleaving manner. This way the resolution of the converter digital output can be significantly increased i.e. the quantising error value reduced. However the analog impairments of parallel converters cause modulation of the output samples which can significantly deteriorate the resultant converter properties. Somehow in many papers describing various structures of Σ-Δ AD converters analysis is limited to the frequency domain, ignoring the fact that Σ-Δ modulators are in fact synchronous voltage to frequency converters. This paper demonstrates how, recognizing the time domain properties of Σ-Δ modulators, the problem of analog impairments of converters can be overcome resulting in a better design of high resolution Σ-Δ AD converters.